The present invention relates to a non-volatile semiconductor storage device, and more particularly, to a non-volatile semiconductor memory device having a charge trapping layer.
As one of memory devices configured as semiconductor integrated circuits, there is a non-volatile semiconductor memory device. The non-volatile semiconductor memory device contains an element in which a memory data retains even if a power supply is powered off. As one example of a conventional non-volatile semiconductor memory device, a memory device containing a floating gate (FG) (hereafter, to be referred to as an FG-type memory device) is known. In the FG-type memory device, a threshold voltage for a read current is changed in accordance with charges accumulated in the floating gate. The-FG type memory device stores the data based on the threshold voltage.
In accompaniment with a request of a very fine structure for the non-volatile semiconductor memory device and a request of matching to a CMOS LSI process, the non-volatile semiconductor memory device is required in which a finer structure is easily formed as compared with the FG-type memory device. As such a non-volatile semiconductor memory device, the non-volatile semiconductor memory device (Patent Literature 1) is known which uses the trapping of charges in a charge accumulation layer contained in an insulating film (hereafter, to be referred to as a charge accumulation layer type memory device).
As one example of the charge accumulation layer type memory device, a MONOS type non-volatile semiconductor memory device is known which uses a MONOS (Metal Oxide Nitride Oxide Semiconductor) cell (Patent Literatures 1, 2). The MONOS cell contains two diffusion layers (Source/Drain Implant) that serve as a drain and a source, respectively, and a memory gate electrode provided through a memory gate insulating film on a channel region between the two diffusion layers. Also, a control gate (select gate) electrode is provided on the side of the memory gate electrode.
FIG. 1 is a sectional view showing a memory cell 101 described in Patent Literature 1. The technique described in Patent Literature 1 is intended to provide a non-volatile semiconductor memory device that has a write/erasure property with a high performance. With reference to FIG. 1, in the memory cell 101, a select gate 118 is formed through a gate insulating film 106 on a P-type well 102 of a semiconductor substrate. Also, on the P-type well 102, a memory gate 117 is formed through a lamination film 115 of a silicon oxide film 115a, a silicon nitride film 115b and a silicon oxide film 115c. The memory gate 117 is adjacent to the select gate 118 through the lamination film 115. An n-type impurity diffusion layer 120 and an n-type impurity diffusion layer 121, which respectively serve as a source and a drain, are formed in regions on both sides of the P-type well 102, namely, on the select gate 118 and the memory gate 117. In a channel region located between the impurity diffusion layer 120 and the impurity diffusion layer 121, impurity concentrations are different between a region 151 that can be controlled by the select gate 118 and a region 152 that can be controlled by the memory gate 117.
The technique described in Patent Literature 1 allows SSI (Source Side Injection) whose write efficiency is excellent. Also, at a time of erasure, a voltage difference is generated between the source diffusion layer and the memory gate to achieve hot hole erasure using BTBT (Band To Band Tunneling). By achieving the hot hole erasure, the technique described in Patent Literature 1 can suppress a use voltage to a low voltage, as compared with a technique in which electrons are pulled out through the use of FN-Tunneling.
FIG. 2 is a sectional view showing a memory cell 200 described in Patent Literature 2. The technique described in Patent Literature 2 is intended to provide a non-volatile semiconductor memory device in which a manufacturing process is easy, a high integration is possible, a property is stable even if a write operation, a read operation and an erase operation are repeated, and an occupation region can be reduced so as to be suitable for a higher performance, and a method of driving the same, and a method of manufacturing the same.
With reference to FIG. 2, the memory cell 200 contains a charge retention film 204, which is laminated on a semiconductor substrate 201 and has a charge retention function. The charge retention film 204 contains a bottom silicon oxide film 204-1, a charge capturing film 204-2 and a top silicon oxide film 204-3. Also, this contains a memory gate electrode 205 formed through the charge retention film 204 on the semiconductor substrate 201. A sidewall gate electrode 207a is insulated from the memory gate electrode 205 by a silicon oxide film 206a, and a sidewall gate electrode 207b is insulated from the memory gate electrode 205 by a silicon oxide film 206b, and the sidewall gate electrode 207a and the sidewall gate electrode 207b are formed on both sides of the memory gate electrode 205. Also, the memory cell 200 has a source impurity diffusion layer 202 adjacent to the sidewall gate electrode 207a and a drain impurity diffusion layer 203 adjacent to the sidewall gate electrode 207b, inside the semiconductor substrate 201.
In the memory cell 200, a semiconductor substrate surface region between the source impurity diffusion layer 202 and the drain impurity diffusion layer 203 becomes a channel region in which a channel of a memory transistor is formed at a time of an operation. The channel region is composed of an inner channel region Ch2 formed on the substantial center thereof, an outer side channel region Ch1 between the inner channel region Ch2 and the source impurity diffusion layer 202, and an outer channel region Ch3 between the inner channel region Ch2 and the drain impurity diffusion layer 203. The inner channel region Ch2 is formed such that a P-type impurity concentration is lower than those of the outer channel region Ch1 and the outer channel region Ch3.
In the technique described in Patent Literature 2, the charge retention film 204 is used under the central memory gate electrode 205, and the electrodes on the sidewalls of both sides (the sidewall gate electrode 207a and the sidewall gate electrode 207b) are used as a selection transistor. In the technique described in Patent Literature 2, each of a memory section 204a and a memory section 204b is used as one memory section. The source impurity diffusion layer 202 and the drain impurity diffusion layer 203 are used while the roles as the drain and the source are switched on the basis of the bit of the memory section 204a or 204b which is read. Both of the electrodes on the sidewalls of both sides (the sidewall gate electrode 207a and the sidewall gate electrode 207b) must function as the selection transistor. For this reason, the outer channel region Ch1 and the outer channel region Ch3 require Leff (effective channel length) under which off leakage can be sufficiently suppressed.
In the memory cell 200 described in Patent Literature 2, even if the hot hole erasure is tried, it is difficult for the generated hole to arrive at the charge retention film 204. For this reason, the technique described in Patent Literature 2 attains the erasure by applying a high voltage to the memory gate electrode 205 and pulling out the electrons through the use of the FN-Tunneling.